The present invention relates to method and apparatus for logical simulation of an operation of a logic circuit, and more particularly to a logical simulation processor which simulates a logic operation of a large scale logic circuit at a high speed. The present invention relates to the, method of simulation disclosed in U.S. Pat. No. 4,899,273, entitled "Simulation Method and a Vector Processor Suitable Therefor" which is incorporated herein by reference. Use of a vector processor for high speed logic simulation of a large scale logic circuit is disclosed in Proceeding of ICCAD 1986, pages 390-393.
A method for introducing a new signal value for increasing the processing speed of logic simulation of a large scale logic circuit and improve the precision thereof has been known. For example, a clock event suppress system for increasing the processing speed by handling a periodically varying signal as a clock signal is disclosed in Proceeding of ICCD 1983, pages 277-280. A signal value is calculated only for an element in the logic circuit to be simulated in which a signal actually varies. In the logic simulation by an event driven algorithm, many signal value changes or events relating to the clock signal for controlling the operation of the logic circuit occur and such signals are represented by special signal values to reduce the quantity of logical simulation or the number of events in the event driven algorithm and increase the processing speed.
In the prior art, it is necessary to clearly define a relation between the signal value newly introduced and all elements of the logic circuit to be simulated, that is, a method for calculating an output signal value from an input signal value based on element functions of the elements in a signal system including the new signal value. The output signal value calculation process by the output signal value calculation method should not be too complex.
In the clock event suppress system, it is necessary to define the logical operation in the signal value system including the clock signal. In this case, logical AND and logical OR of the clock signal and a conventional "1" or "0" signal may be easily defined, but it is not easy to define a method for calculating the output signal value when clock signals are logically ANDed or ORed, or when the clock signal is applied to an element (delay element) which represents a delay by wiring.
For the logical OR or logical AND of the clock signal and the conventional "0" or "1" signal, the output signal value is "0" or equal to the value of the input clock signal, and the logical operation to calculate the output signal value can be readily defined. However, for the logical OR or logical AND of the clock signals, unlike the definition of the logical operation for calculating the output signal value in which conventional "0" or "1" logical signals are applied to a logical OR or logical AND element, it is not easy to define the logical operation in which input clock signals having their periods and phases are employed as input signal values, and an output clock signal value having its period and phase, which may be different from those of input clock signals, are calculated on the basis of the input clock signals. When the clock signal is applied to the delay element, it is necessary to calculate the phase of the clock signal in accordance with the period and phase of the input clock signal and a delay inherent to the delay element and produce the output clock signal having the calculated phase. Thus, an arithmetic operation for calculating the phase is required. Since the output signal appears delayed in the delay element even after a value of the input signal has been changed, it is necessary to hold the period of the output signal for each clock signal. Thus, the method for expressing the output value is complex and also the output signal value calculation method cannot be readily defined. Further, since the logical operation as well as the arithmetic operation are required in calculating the output value, means for attaining the output signal value is complex.
In the prior art, no attention has been paid for a case where the relation between the newly introduced signal value and the element of the logic circuit is not clearly defined or the output signal value calculation based on the above relation is not easily attained, and it is hardly applicable to general logic simulation.